1. Field of the Invention
The present invention relates to a spin-on glass (SOG) composition useful in forming a silicon oxide layer in a semiconductor manufacturing process, to a semiconductor device made thereby, and to a method of forming a silicon oxide layer using the same. More particularly, the present invention relates to a spin-on glass composition containing polysilazane, and its use in forming a silicon oxide layer in a semiconductor device.
2. Description of the Related Art
The design of semiconductor devices has recently made rapid progress. In particular, this progress has required semiconductor devices to function with high operating speed, and to have a large storage capacitance. In order to satisfy such requirements, semiconductor devices with increased density, reliability, and response time are under development.
Integrated circuits typically are manufactured by forming a large number of active devices on a single substrate. After each device is formed and insulated, some of the devices are electrically interconnected during the manufacturing process to accomplish a desirable circuit function. Metal Oxide Semiconductor (MOS) and bipolar VLSI and ULSI devices, for example, have multilevel interconnection structures in which a large number of devices are interconnected. In such a multilevel interconnection structure, the topography of the top layer usually is increasingly irregular and uneven as the number of layers increases.
For example, a semiconductor wafer with two or more metal layers typically is formed as follows. A number of oxide layers, a polycrystalline silicon conductive layer, and a first metal wiring layer are formed on a semiconductor wafer. A first insulation layer then is formed on the resulting structure. Then, a via hole is formed for providing circuit paths to a second metal layer. At this time, the surface of the first insulation layer is uneven because the layers underlying the first insulation layer are uneven. When the second metal layer is directly formed on the first insulation layer, the second metal layer may fracture due to protrusions or cracks in the underlying insulation layer. In addition, there may be a decreased yield of the semiconductor device if the deposition state of the metal layer is poor. Accordingly, the insulation layer typically is planarized before formation of the via hole or the second metal layer that will be formed in a multilevel metal interconnection structure.
Various methods have been developed to planarize the insulation layer. These methods include utilizing a borophosphorous silicate glass (BPSG) layer, which has good reflow characteristic, or an SOG layer and a chemical mechanical polishing (CMP) method. In general, BPSG is widely utilized as an insulation layer material to fill gaps between metal wirings. However, depositing BPSG presents problems because it depends primarily on establishing special deposition parameters for the equipment utilized. In addition, the gases used in the process are expensive and severely toxic.
Furthermore, as the packing density increases and the design rule gradually decreases for manufacturing VLSI having 256 megabits or more, using BPSG as the insulation layer to fill gaps between wirings lowers the yield due to the occurrence of voids and bridges. In addition, an etch stop layer may possibly be damaged during its subsequent formation. Thus, the prior art typically implements a reflowing process and an expensive CMP process to solve these problems.
An insulation layer formed by an SOG layer is known as being manufactured by a simple coating process. This process produces a planar insulation layer. For example, U.S. Pat. No. 5,310,720 (issued to Shin et al.) discloses a method for making a silicon oxide layer. A polysilazane layer is formed, and then the polysilazane layer is heated in an oxygen atmosphere to convert it into a silicon oxide layer. U.S. Pat. No. 5,976,618 (issued to Shunichi Fukuyama et al.) discloses a method in which an inorganic SOG is deposited, and then two step heat treatment processes are implemented to convert the SOG layer into a silicon oxide layer.
The basic backbone structure of polysilazane-based SOG is composed of Si—N, Si—H and N—H bonds. The Si—N bonds are converted into (or substituted with) Si—O bonds by baking under an atmosphere including oxygen and water. A simple spin coating and a simple curing process are performed to convert the SOG layer into the silicon oxide layer. Accordingly, it is an economical method.
Not all of the Si—N bonds, however, are converted to Si—O bonds (see, for example, Japanese Patent Laid-Open No. Hei 11-145286). Accordingly, the silicon oxide layer has different insulating and electrical characteristics when compared to a pure silicon oxide layer such as one formed using a BPSG. layer or a TEOS layer. For these reasons, many have avoided using the SOG layer to form a layer, and then convert it into a silicon oxide insulation layer. In addition, because SOG is deposited by a spin coating method, the thickness of the thus formed silicon oxide layer is not sufficient. This provides insufficient coverage for the conductive layers, such as gate electrodes and metal wirings.
The present Applicants have invented a spin-on glass composition including perhydropolysilazane which can bury a gap between metal wirings of VLSI degree having a high aspect ratio, can bury a gap on a substrate without applying a mechanical planarization, can smooth a surface discontinuities and can produce an oxide layer of a semiconductor device, having substantially the same characteristic as a CVD oxide layer, and filed a patent application concerning an invention entitled “SPIN-ON GLASS COMPOSITION AND METHOD OF FORMING SILICON OXIDE LAYER IN SEMICONDUCTOR MANUFACTURING PROCESS USING THE SAME”, as a Ser. No. 09/686,624, on Oct. 12, 2000, with USPTO, which is now pending.
According to this method, a planar SOG layer is formed on a semiconductor substrate having a stepped portion or surface discontinuities by coating on the semiconductor substrate a spin-on glass composition including polysilazane having the chemical formula of —(SiH2NH2)n— where n represents a positive integer, a weight average molecular weight within the range of about 4,000 to 8,000, and a molecular weight dispersion degree within the range of about 3.0 to 4.0. Finally, the SOG layer is cured to form a silicon oxide layer having a planar surface.
As for the silicon oxide layer, an isolation layer of an STI (shallow trench isolation) structure can be formed on a semiconductor substrate having a stepped portion formed by grooves and protrusions to form an isolation structure, can be illustrated.
The baking step is implemented by two steps of a pre-baking and a main-baking. The pre-baking of the SOG layer is implemented at a temperature within the range of about 100-500° C., more preferably in the range of about 100-400° C. for a period of about 1-5 minutes, more preferably of 2-3 minutes. The main-baking of the SOG layer is implemented at a temperature within the range of about 900-1,050° C.
At this time, the manufactured silicon oxide layer has a good gap filling characteristic for an STI structure including gaps having about 0.1-1 μm. However, according to a wet etching rate test, the etching rate decreases as the temperature of the main-baking increases, and a silicon oxide layer is formed at the surface portion of the silicon substrate and an active region.
FIG. 1 is a cross-sectional view of an oxide formed on an inner surface of a trench. The device illustrated in FIG. 1 is manufactured by the following method. A pad oxide layer is formed on a silicon substrate 100 and then, a nitride layer and a high temperature oxide layer are sequentially formed on the pad oxide layer. The nitride layer is provided as an etch stopping layer for the subsequently implementing chemical mechanical polishing process and the high temperature oxide layer is provided as a hard mask layer.
Next, an anti-reflective layer (not shown) is formed on the high temperature oxide layer by depositing a silicone oxynitride compound (SiON) and a high temperature oxide layer pattern 116 is formed for defining an active pattern by utilizing a photolithography.
The nitride layer and the pad oxide are etched by using the high temperature oxide layer pattern 116 as an etching mask to form a nitride layer pattern 114 and a pad oxide layer pattern 112. Then, an upper portion of the substrate 100 adjacent to the nitride layer pattern 114 is etched to form a trench 118.
Subsequently, an exposed portion of the trench 118 is heat treated under an oxidizing atmosphere to cure a silicon damage induced by an ion impaction of a high energy during the etching process of the trench. Then, a trench inner wall oxide layer 120 is formed at the inner portion of the trench 18 including the bottom and side portions thereof by an oxidation reaction of the exposed silicon with an oxidizing agent.
Next, the SOG composition suggested by the present Applicants is deposited on the semiconductor substrate 100 to fill the trench 118 and to form an SOG layer. Then, the SOG layer is baked. A pre-baking is implemented at a temperature range of about 100-500° C., preferably about 100-400° C. for about 1-5 minutes, preferably for about 2-3 minutes. A main-baking is implemented at a temperature range of about 900-1050° C. to form silicon oxide. Then, an oxide layer 130 burying the trench is manufactured as illustrated in FIG. 1. The oxide layer 130 is formed from the SOG layer. At this time, it is known that the trench inner wall oxide layer 120 at the side wall portion is thicker than that at the bottom portion, as designated by a circle. The oxide compound is thought to be formed by an oxidation reaction of silicon in the substrate 100 with oxygen contained in the oxidizing atmosphere when baking at 1000° C. or more under the oxidizing atmosphere.
The generation of the oxide might induce a shape defect at a dent portion after implementing a CMP process or might change the size of the active region.
The present Applicants have also invented a spin-on glass composition including perhydropolysilazane which can bury a gap between metal wirings of VLSI degree having a high aspect ratio, can bury a gap on a substrate without applying a mechanical planarization, can smooth a surface discontinuities and can produce an oxide layer of a semiconductor device, having substantially the same characteristic as a CVD oxide layer, and filed a patent application concerning an invention entitled “METHOD OF FORMING SILICON OXIDE LAYER IN SEMICONDUCTOR MANUFACTURING PROCESS USING SPIN-ON GLASS COMPOSITION AND ISOLATION METHOD USING THE SAME METHOD”, by the present inventors, Ser. No. 10/278,992, filed on Oct. 24, 2002, with the USPTO, which is now U.S. Pat. No. 6,479,405.